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february 2006 copyright ? alliance semiconductor. all rights reserved. ? as7c4098a 5.0 v 256 k 16 cmos sram 2/21/06, v 1.2 alliance semiconductor p. 1 of 11 features ? pin compatible with as7c4098 ? industrial and commercial temperature ? organization: 262,144 words 16 bits ? center power and ground pins ? high speed - 10/12/15/20 ns address access time - 5/6 ns output enable access time ? low power consumption: active - 990mw/max @ 10 ns ? low power consumption: standby - 55mw/max cmos ? individual byte read/write controls ? easy memory expansion with ce , oe inputs ? ttl- and cmos-compatible, three-state i/o ? 44-pin jedec standard packages - 400-mil soj - tsop 2 ? esd protection 2000 volts ? latch-up current 200 ma logic block diagram 1024 256 16 array (4,194,304) oe ce we column decoder row decoder a0 a1 a2 a3 a4 a6 a7 a8 v cc gnd a12 a5 a9 a10 a11 a14 a15 a16 a17 a13 control circuit i/o1?i/o8 i/o9?i/o16 ub lb i/o buffer pin arrangement for soj and tsop 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 i/o14 i/o13 gnd v cc i/o12 i/o11 i/o10 i/o9 nc a14 a13 a12 a11 a10 a4 ce i/o1 i/o2 i/o3 i/o4 v cc gnd i/o5 i/o6 i/o7 i/o8 we a5 a6 a7 tsop2 21 22 a8 a9 ub lb i/o16 i/o15 2 a1 3 a2 4 a3 1 a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a16 a15 oe a17 44-pin (400 mil) soj selection guide ?10 ?12 ?15 ?20 unit maximum address acces s time 10 12 15 20 ns maximum output enab le access time 5 6 6 6 ns maximum operating current 180 160 140 120 ma maximum cmos standby current 10 10 10 10 ma
? as7c4098a 2/21/06, v 1.2 alliance semiconductor p. 2 of 11 functional description the as7c4098a is a high-performance cmos 4,194,304-bit static random access memory (sram) device organized as 262,144 words 16 bits. it is designed for memory applications where fast data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with ou tput enable access times (t oe ) of 5/6 ns are ideal for high-performance applications. the ch ip enable input ce permits easy memory expansion with multiple-bank memory systems. when ce is high the device enters standby mode. the device is guaranteed not to exceed 55m w power consum ption in cmos standby mode. a write cycle is accompli shed by asserting write enable (we ) and chip enable (ce ). data on the input pins i/ o1?i/o16 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and chip enable (ce ), with write enable (we ) high. the chip drives i/o pins with the data word referenced by the input addr ess. when either chip enable or output enable is inactive, or write enable is active, output dr ivers stay in high-impedance mode. the device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. lb controls the lower bits, i/o1?i/o8, and ub controls the higher bits, i/o9?i/o16. all chip inputs and outputs are ttl- a nd cmos-compatible, and operation is for 5.0v (as7c4098a) supply. the device is available in the jedec standard 400-ml, 44-pin soj, tsop 2 packages. note: stresses greater th an those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indica ted in the operational sections of this specification is not implied. exposure to absolute maximu m rating conditions for extended periods may affect reliability. absolute maximum ratings parameter symbol min max unit voltage on v cc relative to gnd v t1 ?0.50 +7.0 v voltage on any pin relative to gnd v t2 ?0.50 v cc +0.50 v power dissipation p d ?1.5w storage temperature (plastic) t stg ?65 +150 c ambient temperature with v cc applied t bias ?55 +125 c dc current into outputs (low) i out ?20ma truth table ce we oe lb ub i/o1?i/o8 i/o9?i/o16 mode hxxxx high z high z stan dby (i sb , i sb1 ) lhhxx high z high z output disable (i cc ) lxxhh lhl lh d out high z read (i cc ) hl high z d out ll d out d out llx lh d in high z write (i cc ) hl high z d in ll d in d in key: x = don?t care, l = low, h = high.
? as7c4098a 2/21/06, v 1.2 alliance semiconductor p. 3 of 11 * v ih max = v cc + 1.5v for pulse width less than 5 ns. ** v il min = ?1.0v for pulse width less than 5 ns. recommended operating conditions parameter symbol min typical max unit supply voltage v cc (10/12/15/20) 4.5 5.0 5.5 v input voltage v ih * 2.2 ? v cc + 0.5 v v il ** ?0.5 ? 0.8 v ambient operating temperature commercial t a 0? 70 c industrial t a ?40 ? 85 c dc operating characteristics (over the operating range) 1 parameter symbol test conditions ?10 ?12 ?15 ?20 unit notes min max min max min max min max input leakage current |i li | v cc = max v in = gnd to v cc ? 1? 1 ?1?1a output leakage current |i lo | v cc = max ce = v ih or oe = v ih or we = v il v i/o = gnd to v cc ? 1? 1 ?1?1a operating power supply current i cc v cc = max ce < v il , f = fmax, i out = 0 ma - 180 - 160 - 140 - 120 ma standby power supply current i sb v cc = max ce > v ih , f = max -60-55-50-45ma i sb1 v cc = max ce v cc ? 0.2v, v in v cc ? 0.2v or v in 0.2v, f = 0 -10-10-10-10ma output voltage v ol i ol = 6 ma, v cc = min ? 0.4 ? 0.4 ? 0.4 ? 0.4 v4 i ol = 8 ma, v cc = min ? 0.5 ? 0.5 ? 0.5 ? 0.5 v oh i oh = ?4 ma, v cc = min 2.4 ? 2.4 ? 2.4 ? 2.4 ? v 4 capacitance (f = 1mhz, t a = 25 c, v cc = nominal) 4 parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe , ub , lb v in = 0v 6 pf i/o capacitance c i/o i/o v in = v out = 0v 8 pf
? as7c4098a 2/21/06, v 1.2 alliance semiconductor p. 4 of 11 key to switching waveforms read waveform 1 (address controlled) 5,6,8 read cycle (over the operating range) 2,8 parameter symbol ?10 ?12 ?15 ?20 unit notes min max min max min max min max read cycle time t rc 10 ? 12?15?20? ns address access time t aa ? 10 ?12?15?20ns chip enable (ce ) access time t ace ? 10 ?12?15?20ns output enable (oe ) access time t oe ? 5 ?6?6?6ns output hold from address change t oh 3 ? 3?3?3?ns4 ce low to output in low z t clz 3 ? 3?3?3?ns3, 4 ce high to output in high z t chz ? 5 ?6?7?9ns3, 4 oe low to output in low z t olz 0 ? 0?0?0?ns3, 4 oe high to output in high z t ohz ? 5 ?6?7?9ns3, 4 lb , ub access time t ba ? 5 ?6?7?8ns lb , ub low to output in low z t blz 0 ? 0?0?0?ns lb , ub high to output in high z t bhz ? 5 ?6?7?9ns power up time t pu 0 ? 0?0?0?ns4 power down time t pd ? 10 ?12?15?20ns 4 undefined/don?t care falling input rising input t oh t aa t rc t oh data out address data valid previous data valid
? as7c4098a 2/21/06, v 1.2 alliance semiconductor p. 5 of 11 read waveform 2 (ce , oe , ub , lb controlled) 5,7,8 write cycle (over the operating range) 9 parameter symbol ?10 ?12 ?15 ?20 unit note min max min max min max min max write cycle time t wc 10?12?15?20? ns chip enable (ce) to write end t cw 7?8?10?12?ns address setup to write end t aw 7?8?10?12?ns address setup time t as 0?0?0?0?ns write pulse width (oe = high) t wp1 7?8?10?12?ns write pulse width (oe = low) t wp2 10?12?15?20? ns write recovery time t wr 0?0?0?0?ns address hold from end of write t ah 0?0?0?0?ns data valid to write end t dw 5?6 7?9?ns data hold time t dh 0?0?0?0?ns3, 4 write enable to output in high-z t wz 25262729ns3, 4 output active from write end t ow 3?3?3?3?ns3, 4 byte enable low to write end t bw 7?8?10?12?ns3, 4 data valid t rc t aa t blz t ba t oe t olz t oh t ohz t chz t bhz t ace t clz address oe ce lb , ub data out
? as7c4098a 2/21/06, v 1.2 alliance semiconductor p. 6 of 11 write waveform 1(we controlled) 9 write waveform 2 (ce controlled) 9 address ce lb , ub we data in data out t wc t cw t bw t aw t as t wp t dw t dh t ow t wz t ah data undefined high z data valid t wr address ce lb , ub we data in t wc t cw t bw t dw t dh t ah t as t aw data valid t wr t wp
? as7c4098a 2/21/06, v 1.2 alliance semiconductor p. 7 of 11 write waveform 3 9 ac test conditions notes 1during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 for test conditions, see ac test conditions , figures a and b. 3t clz and t chz are specified with c l = 5pf as in figure b. transition is me asured 500mv from st eady-state voltage. 4 this parameter is guaranteed, but not tested. 5we is high for read cycle. 6ce and oe are low for read cycle. 7 address valid prior to or coincident with ce transition low. 8 all read cycle timings are referenced from the last valid address to the fi rst transitioning address. 9 all write cycle timings are referen ced from the last valid address to the firs t transitioning address. 10 c = 30 pf, except on high z and low z parameters, where c = 5 pf. address ce lb , ub we data in t wc t cw t bw t wp t dw t dh t wz t ah data out data undefined high z high z t as t aw data valid t wr - output load: see figure b. - input pulse level: gnd to v cc - 0.5v. see figure a. - input rise and fall times: 2 ns. see figure a. - input and output timing reference levels: 1.5v. 10% 90% 10% 90% gnd v cc - 0.5v 2 ns figure a: input pulse 255 ? c 10 480 ? d out gnd +5.0v figure b:5.0v output load 168 ? d out +1.728v thevenin equivalent:
? as7c4098a 2/21/06, v 1.2 alliance semiconductor p. 8 of 11 package dimensions 44-pin tsop 2 min (mm) max (mm) a 1.2 a 1 0.05 0.15 a 2 0.95 1.05 b 0.30 0.45 c 0.12 0.21 d 18.31 18.52 e 10.06 10.26 h e 11.68 11.94 e 0.80 (typical) l 0.40 0.60 d h e 1234567891011 121314 44 43424140393837363534333231 1516 3029 1718 1920 272625 c l a 1 a 2 e 44-pin tsop 2 0?5 21 24 22 23 e a b 44-pin soj 400 mils min(mils) max(mils) a 0.128 0.148 a1 0.025 - a2 0.105 0.115 b 0.026 0.032 b 0.015 0.020 c 0.007 0.013 d 1.120 1.130 e 0.370 nom e1 0.395 0.405 e2 0.435 0.445 e 0.050 nom seating plane 44-pin soj 28 pin 1 d e e2 e1 a1 b b a a2 e c
? as7c4098a 2/21/06, v 1.2 alliance semiconductor p. 9 of 11 note: add suffix ?n? to the above pa rt numbers for lead free parts. (e x : as7c4098a - 10tcn) ordering codes package version 10 ns 12 ns 15 ns 20 ns soj 5.0v commercial as7c4098a-10jc as7c4098a-12jc as7c4098a-15jc as7c4098a-20jc 5.0v industrial as7c4098a-10ji as7c4098a-12ji as7c4098a-15ji as7c4098a-20ji tsop 2 5.0v commercial as7c4098a-10tc as7c4098a-12tc as7c4098a-15tc as7c4098a-20tc 5.0v industrial as7c4098a-10ti as7c4098a-12ti as7c4098a-15ti as7c4098a-20ti part numbering system as7c 4098a ?xx j or t x x sram prefix device number access time packages: j: soj 400 mil t: tsop 2 temperature ranges: c: commercial , 0c to 70c i: industrial, ?40c to 85c n = lead free parts
? as7c4098a 2/21/06, v 1.2 alliance semiconductor p. 10 of 11 revision history rev. no. history revised date v1.0 initial release 11/08/04 v1.1 included i cc , i sb & i sb1 parameters 05/27/05 corrected the following: t oe , v ih , v ol & t wz v1.2 removed the title ?preliminary information? 02/21/06
alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel: 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? alliance semiconductor all rights reserved part number: as7c4098a document version: v 1.2 ? copyright 2003 alliance semiconductor corp oration. all rights reserved. our three-po int logo, our name and intelliwatt are tr ademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of th eir respective companies. alliance reserve s the right to make changes to this document and its products at any time without notice. alliance assumes no respon sibility for any errors that ma y appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product desc ribed herein is under development, signifi cant changes to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customer s and users, and is not intende d to operate as, or provide, any guarantee or warrantee to any user or cust omer. alliance does not assume any responsib ility or liability arising out of the app lication or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringe ment of any intellectual property rights, except as express ag reed to in alliance's terms and conditions of sale (which are available from alliance). all sa les of alliance products are made exclusively according to allian ce's terms and conditions of sale. the purchase of products from allianc e does not convey a license under any pate nt rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. allianc e does not authorize its products for use as critical compone nts in life-supporting systems where a malfunction or failure may reasonably be expected to resu lt in significant injury to the user, and the inclusion of all iance products in such life- supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all clai ms arising from such use. as7c4098a ? ?

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